The release notes hints at the existence of a newer 1. What you very helpfully included was one of the possibilities I’d already tried as dsdtjmb. Try TheKings suggested changes and report back. Net cannot verify the validity of the statements made on this site. It seems like bits [1:

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It is not a data table containing some form of initial register values. Therefore, I chose to set register df[6] to cause the option ROM to liux without detecting drives.

Then i adapted the entry to: The second part of the problem is to modify the option ROM given you already know how to jmb36xx the chip. These configuration registers seem to control the hardware directly. Thus it seems like setting 0x41[7: It’s a personnal request, could you please upload your patched dsdt lappy I think we’ve the same Asus M50svit much needed for SL.

Those three bytes used to be a function call to liinux function that would read a byte from the PCI configuration space register diand return the result in cl.


Or do I just leave it alone? For details and our forum data attribution, retention and privacy policy, see here.

JMicron JMB363 Add-on Card AHCI mode

Which of these mmb36x I need anyway? Register df[6] is used by the option ROM code at offset 0x This, however, was fixed by JMicron by a newer driver so I know the drive and the controller are completely cabable of doing their thing. What happened to the KB article about disk mirroring?

Posted September 14, NCQ is working here. Runtime corruption detected on eSATA, fsck will be forced on next mount.

[ubuntu] Ubuntu and Jmicron JMB eSata

This changes mov cl, 0x02 to mov cl, 0x Besides that I got two informations for you about the built-in raidcontroller. You have loads of other changes in your JMB entry, maybe thats the cause of your problems.

I replaced 3 bytes with b1 02 I did not experiment with the values of these bits except for toggling bit 6. One tip for those who used jmicronata.


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Any pointers would be appreciated. The problems with configuration register 0x are more problematic. Problems Only modifying register df[1: Thank you so much ApexDE.


Here is the link: I wasn’t expecting this in AHCI mode. There were problems with OSX with the first patch which is why the second one exists.

This seems to put the controller in AHCI mode. I have a similar card to add support for PATA drives.

Those connected at boot were not detected.