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Written By eli on March 22nd, The device-driver is designed to be architecture independent but PCIe communication has only been tested from x Inferred RAM and mux.
User programs have to access to this information. Xillybus gives you the data directly through a device file interface.
CONFIG_ALTERA_PCIE_CHDMA: Altera PCI Express Chaining DMA driver
Plus copying a file or two. Jamey Hicks 1, 1 11 Verilog source code is alteta published, as the IP core is licensed against fees. Written By eli on April 25th, What packet size and transfer size did you use for throughput calculations?
Does anyone any idea where I can found some source? No kernel programming will be necessary either.
Thanks Eli for the response on Xillybus throughput. This is not a research project, but rather an implementation of an IP core. All that is needed, is to ilnux a certain kernel module against the headers of the running Linux kernel.
As for the throughput: This comment section is closed.
Post as a guest Name. According to schedule, I would say. Maybe with configurable word widths?
Linux Kernel Driver DataBase: CONFIG_ALTERA_PCIE_CHDMA: Altera PCI Express Chaining DMA driver
It contains all of the information that you would need to map in a PCIe device and create device files that user space programs can use.
Having a way to push data from the PC to the FPGA and pull other data back would be so useful not only for testing, but it could also be the actual application. Written By Venice Lim on February 8th, Written By Smith on February 29th, Written By eli on May 30th, Written By eli on February 8th, It arrives as packets which you need to handle one by one with a state machine you develop.
Porting to Altera is currently not planned.